Generating transmission-code compliant test sequences

ABSTRACT

Disclosed herein are exemplary methods, apparatus, and systems for generating test sequences that can be used to evaluate high-speed circuit pathways. The disclosed methods, apparatus, and systems can be used, for example, in a printed circuit board or integrated circuit design flow to analyze signal integrity or other electrical behavior. For example, in one exemplary embodiment, a sequence of code words to be input on a circuit channel is determined in a nonrandom manner. In this embodiment, the sequence of code words complies with a transmission code (for example, the 8b10b transmission code) and is designed to cause the output voltage of the channel to be reduced during a time period in which the channel outputs a logic high value.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional PatentApplication No. 60/927,163, entitled “Worst-Case Pattern Generation forLinear Signal Channels,” and filed on May 1, 2007. U.S. ProvisionalPatent Application No. 60/927,163 is hereby incorporated herein byreference.

TECHNICAL FIELD

This application relates generally to the field of analyzing the signalintegrity of signals using an electronic design automation softwaretool.

BACKGROUND

Signal integrity is an important consideration in designing today'shigh-speed circuits and systems. To help optimize the performance ofsuch circuits and systems, simulation-based analysis techniques thatpredict the signal integrity of the various circuit paths of the systemare often used before the circuit is ever manufactured. In thissimulation environment, signal integrity problems (caused, for example,by noise, crosstalk, or intersymbol interference) can be identifiedearly and the design modified if necessary.

One area where simulation-based signal integrity analysis isincreasingly used is in the design of printed circuit boards (“PCBs”).When designing PCB layouts, for example, it is often desirable toanalyze the signal integrity of the channels between the integratedcircuits (“ICs”) on the board or between various other circuitcomponents of the PCB. In particular, the signal integrity of a channelbetween a driver and a buffer of a PCB layout is desirably analyzed sothat the bit error rate (“BER”) and eye diagram for the channel can beaccurately predicted and analyzed before the PCB is manufactured.Accordingly, improved methods for analyzing the signal integrity ofchannels in a PCB layout or integrated circuit design are desired.

SUMMARY

Disclosed herein are exemplary methods, apparatus, and systems forgenerating test sequences that can be used to evaluate high-speedcircuit pathways. The disclosed methods, apparatus, and systems can beused, for example, in a printed circuit board or integrated circuitdesign flow to analyze signal integrity or other electrical behavior.The disclosed methods, apparatus, and systems should not be construed aslimiting in any way. Instead, the present disclosure is directed towardall novel and nonobvious features and aspects of the various disclosedmethods, apparatus, systems, and equivalents thereof, alone and invarious combinations and subcombinations with one another. The presentdisclosure is not limited to any specific aspect or feature, orcombination thereof, nor do the disclosed methods, apparatus, andsystems require that any one or more specific advantages be present orproblems be solved.

Among the disclosed embodiments are methods for generating a testsequence of bits that can be used, for example, to test the electricalbehavior of a circuit channel. In one exemplary method, a sampled pulseresponse for the circuit channel is divided into a series of bit groups.The respective lengths of the bit groups in the series can comply with atransmission code (for example, the 8b10b transmission code). In thisembodiment, possible code word types corresponding to the bit groups ofthe sampled pulse response are determined. The possible code word typescan also comply with the transmission code. Further, cumulative costsare computed for one or more of the possible code word types. Forexample, the cumulative cost for a respective code word type canindicate how effective a sequence comprising a code word of therespective code word type together with one or more other code words isat altering the intended output of the circuit channel when the sequenceis included in the test sequence. Further, in this embodiment, the testsequence is generated by selecting a sequence of code words based atleast in part on the determined cumulative costs. The test sequence canbe stored on one or more computer-readable media. In certainimplementations, local costs for the one or more of the possible codeword types are also computed. For example, the local cost for arespective code word type can indicate how effective a code word of therespective code word type is at altering an intended output of thecircuit channel when the code word is included in the test sequence. Incertain implementations, the cumulative cost for the respective codeword type is computed in part from the local costs of the other codewords in the sequence. To compute the local costs, possible code wordsof a respective code word type can be evaluated to determine which ofthe possible code words produces the lowest local cost for thatrespective code word type. In some implementations, cumulative costs ofsequences that represent full test sequences are determined. The fulltest sequence producing the lowest cumulative cost can then be selectedas the test sequence. In certain implementations, the code word of therespective code word type is a first code word in the sequence and asecond code word is selected from among multiple possible second codewords to be sequentially adjacent to the first code word. The multiplesecond code words can be of code word types different than the firstcode word. In some implementations, allowable transitions between thepossible code word types are determined, and the multiple possiblesecond code words are determined based at least in part on the allowabletransitions. Further, the multiple possible second code words can haveassociated cumulative costs. The selection of the second code word canthen be performed by selecting the second code word having the lowestassociated cumulative cost. In some implementations, the bit groups intowhich the sampled pulse response is divided are oriented in a firstorientation relative to a leading bit in the sampled pulse response, andthe test sequence generation method is performed for one or more otherbit group orientations relative to the leading bit. In certainimplementations, the sampled pulse response is generated by simulatingapplication of a single pulse to the circuit channel and dividing theresulting pulse response into samples. The samples can be determined,for instance, according to a bit rate at which the circuit channel is tooperate. Furthermore, the sampled pulse response used with embodimentsof the method can be an inverted or noninverted sampled pulse response.In certain implementations, the test sequence generated is one thatminimizes an eye opening of an eye diagram displaying a representationof the circuit channel's response to the test sequence.

In other disclosed embodiments, a sequence of code words to be input ona circuit channel is determined in a nonrandom manner. In particularimplementations, the sequence of code words determined complies with atransmission code (for example, the 8b10b transmission code) and isdesigned to cause the output voltage of the channel to be reduced duringa time period in which the channel outputs a logic high value. Thesequence of code words can be stored on one or more computer-readablemedia. The sequence of code words generated can, in some embodiments, bethe worst case sequence. For example, the sequence of code words can bea sequence which minimizes the eye opening of an eye diagram thatdisplays a representation of the circuit channel's response to thesequence of code words. In some embodiments, the act of determining thesequence includes dividing a sampled pulse response for the circuitchannel into bit groups (for example, bit groups having lengthscomplying with the transmission code). In certain embodiments, the actof determining the sequence includes identifying possible code wordtypes for the bit groups of the divided sampled pulse response. In someembodiments, the act of determining the sequence includes computing avalue indicative of the impact a candidate code word has on reducing theoutput voltage of the circuit channel when the candidate code word isincluded in the sequence. The act of determining the sequence can alsoinclude computing a value indicative of the impact a subsequence of codewords has on reducing the output voltage of the circuit channel when thesubsequence of code words is included in the sequence. The act ofdetermining the sequence can also include evaluating a code word in thesequence, and selecting a sequence of code words to precede the codeword from among multiple possible sequences of code words. The selectioncan be based, for example, at least in part on the impact a respectiveone of the multiple possible sequences has on the output voltage of thecircuit channel when the respective one of the multiple possiblesequences is included in the sequence. In other embodiments, the act ofdetermining the sequence includes evaluating individual code words forpossible inclusion in the sequence, and selecting one or more of thecode words for inclusion in the sequence based at least in part on theeffect the one or more of the code words have on the output voltage ofthe circuit channel when the code words are included in the sequence.

In still other disclosed embodiments, alternative methods for generatinga test sequence of bits for testing the electrical behavior of a circuitchannel are disclosed. In one exemplary embodiment, a test sequenceunconstrained by any transmission code is divided into a series of bitgroups. The lengths of the bit groups in the series can comply with atransmission code (for example, the 8b10b transmission code). In thisembodiment, a first bit group in the series is evaluated for compliancewith the transmission code. If the first bit group is determined not tocomply with the transmission code, one or more bits in the first bitgroup are modified so that the first bit group complies with thetransmission code. The modified first bit group can be stored on one ormore computer-readable media. In certain embodiments, a second bit groupin the series (for example, a second group adjacent to the first bitgroup) is evaluated for compliance with the transmission code. If thesecond bit group is determined not to comply with the transmission code,one or more bits in the second bit group can be modified so that thesecond bit group complies with the transmission code and stored on theone or more computer-readable media. In particular embodiments, when thefirst bit group has a neutral disparity, the method further includedetermining an initial disparity for the first bit group. Thedetermination can be based, for example, at least in part on a disparityof the second bit group. In some embodiments, the remaining bit groupsin the series are sequentially evaluated for compliance with thetransmission code. Respective ones of the remaining bit groups canmodified if they do not comply with the transmission code and stored onthe one or more computer-readable media. In some embodiments, the testsequence unconstrained by any transmission code is generated as part ofthe method. For example, the act of generating the test sequenceunconstrained by any transmission code can include simulatingapplication of a single pulse applied to the circuit channel in order togenerate a pulse response. The pulse response can be divided intosamples, thereby generating a sampled pulse response. The samples of thesampled pulse response can be determined according to a bit rate atwhich the circuit channel will operate and have a polarity and amagnitude. Test sequence bits having polarities opposite to thepolarities of corresponding samples in the sampled pulse response can beassigned to the unconstrained test sequence. Furthermore, in particularimplementations, the first bit group corresponds to a position in thetest sequence adjacent to the largest value in a sampled pulse responseof the channel.

Any of the disclosed methods can be implemented as computer-readablemedia comprising computer-executable instructions for causing a computerto perform the methods. Any of the disclosed methods implemented in acomputer environment can also be performed by a single computer or via anetwork. Further, computer-readable media storing test sequences or testsequence values (or any other final or intermediate results) produced byany of the disclosed methods are also disclosed.

The foregoing and other objects, features, and advantages of theinvention will become more apparent from the following detaileddescription, which proceeds with reference to the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graph showing an exemplary pulse response of a signalchannel under consideration.

FIG. 2 is a graph showing an exemplary sampled pulse response generatedfrom the pulse response of FIG. 1.

FIG. 3 is a graph showing an exemplary inverted sampled pulse responsegenerated from the sampled pulse response of FIG. 2.

FIG. 4 is a schematic block diagram showing code word types and allowedtransitions between the code word types according to an exemplarytransmission code.

FIG. 5 is an exemplary representation showing an arrangement of possiblecode word types relative to bit groups in a sampled pulse response asmay be used to generate a test sequence using embodiments of thedisclosed technology.

FIG. 6 illustrates the use of a representation according to FIG. 5 aspart of an exemplary test sequence generation procedure. In particular,FIG. 6 illustrates the process of determining local costs of code wordtypes according to an exemplary embodiment of the disclosed technology.

FIG. 7 also illustrates the use of a representation according to FIG. 5as part of an exemplary test sequence generation procedure. Inparticular, FIG. 7 illustrates the process of determining cumulativecosts of code word types according to an exemplary embodiment of thedisclosed technology.

FIG. 8 is a schematic block diagram of a distributed computer networkthat can be used to perform any of the disclosed methods.

FIG. 9 is a schematic block diagram of another distributed computernetwork that can be used to perform any of the disclosed methods.

FIG. 10 is a flowchart showing an exemplary application of the computernetworks of FIG. 8 or FIG. 9.

FIG. 11 is a flowchart of a first exemplary embodiment for generatingtest sequences.

FIG. 12 is a flowchart of a second exemplary embodiment for generatingtest sequences.

DETAILED DESCRIPTION

Disclosed herein are exemplary methods, apparatus, and systems formodeling and evaluating high-speed signals that can be used, forexample, in a printed circuit board (“PCB”) or integrated circuit (“IC”)design flow to analyze signal integrity. The disclosed methods,apparatus, and systems should not be construed as limiting in any way.Instead, the present disclosure is directed toward all novel andnonobvious features and aspects of the various disclosed methods,apparatus, systems, and equivalents thereof, alone and in variouscombinations and subcombinations with one another. The presentdisclosure is not limited to any specific aspect or feature, orcombination thereof, nor do the disclosed methods, apparatus, andsystems require that any one or more specific advantages be present orproblems be solved.

Although the operations of some of the disclosed methods, apparatus, andsystems are described in a particular, sequential order for convenientpresentation, it should be understood that this manner of descriptionencompasses rearrangement, unless a particular ordering is required byspecific language set forth below. For example, operations describedsequentially may in some cases be rearranged or performed concurrently.Moreover, for the sake of simplicity, the figures may not show thevarious ways in which the disclosed methods, apparatus, and systems canbe used in conjunction with other methods, apparatus, and systems.Additionally, the description sometimes uses terms like “generate” and“determine” to describe the disclosed methods. These terms arehigh-level abstractions of the actual operations that are performed. Theactual operations that correspond to these terms may vary depending onthe particular implementation and are readily discernible by one ofordinary skill in the art.

The disclosed embodiments can be used to generate test pattern sequencesfor testing and evaluating the signal integrity on channels (forexample, traces, vias and/or other forms of interconnect between adriver and a receiver) in a PCB layout. For example, the sequencesgenerated can produce the worst or near worst eye openings on an eyediagram (often used to provide a visual display of the signal quality ona channel being analyzed over many transitions). The disclosedtechnology is not limited to PCB layout analysis, however, and can beused to evaluate interconnects, vias, and other wires in a wide varietyof circuits (for example, application-specific integrated circuits(“ASICs”) (including mixed-signal ASICs), systems-on-a-chip (“SoCs”), orprogrammable logic devices (“PLDs”), such as field programmable gatearrays (“FPGAs”)). The techniques can also be used to create sequencesused to evaluate power-integrity effects on a channel.

Any of the methods or techniques described herein can be performed usingsoftware that comprises computer-executable instructions for causing acomputer to perform the methods or techniques stored on one or morecomputer-readable media. Such software can comprise, for example, anelectronic-design-automation (“EDA”) software tool, such as a signalintegrity tool. The Hyperlynx tool available from Mentor GraphicsCorporation is one example of a suitable software tool. Any suchsoftware can be executed on a single computer or on a networked computersystem (for example, via the Internet, a wide-area network, a local-areanetwork, a client-server network, or other such network). For clarity,only certain selected aspects of the software-based implementations aredescribed. Other details that are well known in the art are omitted. Forexample, it should be understood that the disclosed technology is notlimited to any specific computer language, program, or computer and thatthe disclosed technology can be implemented using any commerciallyavailable computer. Because such computer hardware is well known in theart, the computer hardware is not described in further detail.

One or more test sequences or intermediate results produced by any ofthe disclosed methods, apparatus, and systems can also be stored on oneor more computer-readable media as part of the described methods andtechniques and are considered to be within the scope of this disclosure.Computer-readable media storing such test sequences or intermediateresults may be accessed and used by a single computer or a networkedcomputer.

Any of the disclosed methods can also be used to generate test sequencesfor use in a computer simulation environment wherein the test sequencesare applied to representations of circuits which are stored on one ormore computer-readable media. For example, the disclosed methodstypically use circuit design information (for example, PCB layoutinformation (such as a .HYP file), device models (such as IBIS models),netlists, GDSII descriptions, or HDL descriptions (such as a Verilog orVHDL descriptions), or the like) stored on computer-readable media. Incertain embodiments, the circuits to be simulated are instantiated asSPICE or Eldo models for simulation. For presentation purposes, thepresent disclosure sometimes refers to circuit components by theirphysical counterparts (for example, drivers, channels, signals, andother such terms). It should be understood, however, that any suchreference not only includes the physical components but alsorepresentations of such circuit components and signals on the componentsas are used in computer-implemented signal integrity analysisenvironments.

Generating Test Sequences

Described below are two representative embodiments for generating testsequences for testing electrical behavior (e.g., the signal integrity)of channels between drivers and receivers in a PCB layout. The resultingtest sequences can be used, for example, in a simulation tool used toanalyze the signal integrity of channels in a PCB layout. As noted, thedescribed methods can be used to generate sequences for other circuitenvironments as well. In general, the test sequences desirably representthe “worst-case” scenario for bit sequences on the channel. It is to beunderstood that the term “worst case” does not necessarily refer to theabsolute worst case, but encompasses test sequences that cause theoutput level (voltage) of the channel to be altered from its idealoutput level by other amounts (for example, within 5% of its worstpossible performance, 10% of its worst possible performance, or otherdesired figure).

Furthermore, certain implementations of the described embodimentsgenerate test sequences in a nonrandom fashion. For example, some of theimplementations of the disclosed embodiments generate test sequence byevaluating possible code words to include in a test sequence accordingto certain criterion or figures of merit that indicate the desirabilityof including respective code words in the test sequence.

Furthermore, the described embodiments can be used to generate sequencesfor circuits designed to operate according to a certain transmissioncode (also referred to as a line code). For illustrative purposes, theembodiments are described in the context of the 8b10b transmission code,though it is to be understood that the methods can be readily adaptedfor use with other transmission codes. 8b10b transmission codes arediscussed in more detail in Widmer A. X., Franaszek P. A., “ADC-Balanced, partitioned-block, 8b/10b transmission code,” IBM J. Res.Development, Vol. 27, No 5, September 1983, pp. 440-451.

FIRST ILLUSTRATIVE EMBODIMENT

In certain implementations of the first illustrative embodiment, themethod for generating a test sequence uses the inverted sampled pulseresponse (Q(k), k=1 . . . N) of the channel under consideration. Theinverted sampled pulse sequence can be obtained, for example, byperforming a circuit simulation of the channel (for example, usinganalytical models of the channel, SPICE models, IBIS models,transistor-level models, ideal voltage source models, or other suchmodels). In other implementations, the pulse response is measured from atest chip or other physical chip implementing the channel underconsideration. It should be understood that the noninverted sampledpulse response can be used with any of the test sequence generationmethods described herein. In such cases, the direction in which the testsequence is generated relative to pulse response will ordinarily bereversed.

According to one exemplary implementation, the pulse response is assumedto be a factor 0.5 of the difference between the channel's response to asingle bit pulse (for example, representing the sequence “ . . .010000000000000 . . . ”) and the constant level corresponding to theprolonged logical state “0”. In other implementations, the pulseresponse can be scaled using different factors or values. Because thestart and end level of the pulse response is the same, the differencecan be defined such that it starts and ends at a zero level, asillustrated by pulse response 110 shown in graph 100 of FIG. 1. Incertain implementations, the samples of the pulse response are takenaccording to the bit rate, one sample per bit. FIG. 2 shows a graph 200wherein samples 212 within a pulse response 210 are illustrated atintervals along the time axis corresponding to the bit rate of thechannel under consideration.

In certain implementations, the input to the channel under considerationis assumed to be a two-level (binary) signal, also sampled with the bitrate. In the illustrated implementation, for example, the channel'sinput is assumed to have the following possible values: x(i)=+1(corresponding to logical “1”) or −1 (corresponding to logical “0”). Inthis implementation, vertical scaling does not affect the solution.

The sampled output of the channel y(k) can be computed as a convolutionbetween the channel's input x(k) and the response P(k), both sampledaccordingly. For example, in certain desirable implementations, thefollowing expression is used to determine the sampled output of thechannel:

$\begin{matrix}{{y(k)} = {\sum\limits_{i = 1}^{k}{{P\left( {k - i} \right)}{x(i)}}}} & (1)\end{matrix}$

To simplify considerations, the sampled response P(k) can be inverted intime, thus producing an inverted sampled pulse response (Q(k)), such asinverted sampled pulse response 310 with samples 312 shown in graph 300of FIG. 3. According to one exemplary implementation, the position ofthe largest positive peak in the response is denoted as n_(max):Q(n_(max))>|Q(n)|, n≠n_(max). In FIG. 3, the corresponding maximumsample value is shown with arrow 320.

Determining Unconstrained Test Sequences Representing the “Worst Case”

The system output can now be represented as:

$\begin{matrix}{{y(k)} = {\sum\limits_{i = 1}^{k}{{Q(i)}{{x(i)}.}}}} & (2)\end{matrix}$

From Expression (2), an unconstrained combination of input pulses x(k)that reduces the output at its last sample value y(N) can be found. Forexample, Expression (2) can be used to determine a test sequence thatrepresents the “worst case” sequence. According to one exemplaryimplementation, one can assume that a logical “1” (the value intended tobe output from the channel) corresponds to the level “high.” The valueat the pulse maximum (arrow 320) can then be assigned to the value “+1”.That is, the input value x(n_(max)) can be assigned to “+1” to representthe logical “1”. In one implementation, to find the unconstrained worstcase sequence, the values of the rest of the input bits (x(n)) can bechosen arbitrarily so as to minimize (or otherwise reduce to a desirablelevel) the total output. For example, the following expression can beused:

$\begin{matrix}{{\min \left( {y(N)} \right)} = {\min {\sum\limits_{n = 1}^{N}{{Q(n)}{{x(n)}.}}}}} & (3)\end{matrix}$

Because x(n) is either +1 or −1, the minimum can be reached if, wheneverpossible, Q(n) and x(n) have opposite signs. Hence, in one exemplaryimplementation:

$\begin{matrix}{{x\left( {n \neq n_{\max}} \right)} = \left\{ \begin{matrix}{{- 1},{{Q(n)} \geq 0}} \\{{+ 1},{{Q(n)} < 0.}}\end{matrix} \right.} & (4)\end{matrix}$

From Expression (4):

$\begin{matrix}{{y_{\min}(N)} = {{Q\left( n_{\max} \right)} - {\sum\limits_{n \neq n_{\max}}{{{Q(n)}}.}}}} & (5)\end{matrix}$

The above procedure can be applied to the samples of Q(n) directly. Anexample is shown in Table 1 below. In Table 1, the first columnindicates the sample index (n), the second column indicates the value ofQ(n) at the corresponding sample number, and the third column representsthe value of the input bit in the corresponding position of the inputsequence that would produce the unconstrained worst case sequenceaccording to Expression (3). The leading bit (corresponding to the bitat n_(max)) is shown in bold in the double-lined cell.

TABLE 1 Inverse Sampled Response and the Worst Case Sequence

8b 10b Sequence Constraints

As noted above, in certain implementations, it is desirable to generatethe worst case sequence that complies with a given transmission code(for example, the 8b10b, 4B5B, 6B8B, 64B66B, or other suitabletransmission code). For illustrative purposes only, the disclosedtechnology is described as being applied to the 8b10b transmission code.It should be understood that the disclosed technology is readilyadaptable to a wide variety of other transmission codes.

For the 8b 10b protocol, and according to one exemplary embodiment ofthe disclosed technology, the following constraints are applied: (1) abit group's individual disparity can only be 2, 0, or +2; (2) for asequence of bit groups, the running disparity must alternate; and (3)the running length of any series of bits cannot exceed 5. Theseconstraints are discussed in greater detail in the following paragraphs.It should be understood that when the disclosed techniques are appliedto other transmission codes, other criteria may be adapted for thosecodes. Furthermore, while the embodiment described herein applies allthree of the constraints, other embodiments use only or one or two (inany combination) of the constraints.

According to the 8b 10b transmission code, the bit stream is dividedinto alternating bit groups of 6 and 4 bits. For each group, a disparitycan be defined. In one implementation, the disparity is a number showingthe balance between logical “1s” and “0s” in a bit group. If the bitgroup has an equal number of “1” and “0”s, its disparity is zero. Sincethe number of bits in a bit group is even, the smallest nonzerodisparity will be either “−2” or “+2.” For example, the bit group “0101”has “0” disparity, “1101” has “+2” disparity, and “0100” has “−2”disparity. Furthermore, in this exemplary embodiment, a bit group is notpermitted to have a larger disparity than “+2” or “−2.”

A running disparity builds by accumulating the individual disparities(sometimes referred to as the “partial disparities”) of the bit groupsconsidered so far. Furthermore, and according to a particularimplementation, an initial running disparity can be set to either a “+1”or “−1.” According to the running disparity constraints introducedabove, a bit group having a negative running disparity is to be followedby a bit group having a neutral (“0”) or positive (“+2”) disparity.Similarly, a bit group having a positive running disparity is to befollowed by a group having a neutral (“0”) or negative (“−2”) disparity.The subsequent group's disparity can be added to the existing runningdisparity, resulting in an updated running disparity. The updatedrunning disparity can then be associated with the subsequent group.Thus, if the initial running disparity is “−1” and the subsequent groupis “+2,” the running disparity value changes from “−1” to “+1” and thesubsequent group is said to have a running disparity of “+1.” In certainimplementations, a group with a neutral disparity does not change thevalue of the running disparity.

Running length indicates the number of “1”s or “0”s standing in a row.Because of the disparity considerations mentioned above, no group mayhave five “1”s or five “0”s. However, when the groups are concatenated,there may occasionally be five or even six identical bits in a row. Forthe embodiment following the constraints introduced above, a runninglength of six is avoided because such a running length is not allowed.

In certain implementations, the disparity and running length rules areinvariant to a time inversion. For example, for sequences complying withthe 8b10b protocol, when the sequence is presented in an inverse order,the inverted sequence will also be 8b10b compliant. Based on thisobservation, it follows that one can generate the sequences bypropagating the disparity and running length rules in either direction,into the “future” or into the “past” or even by starting the building ofthe sequence at some point “in the middle.”

Building Worst Case 8b10b Sequences

In one exemplary implementation, it is desirable to make the smallestnumber of modifications to the unconstrained worst case sequence inorder to create a 8b 10b compliant sequence. It will ordinarily benecessary, however, to make some adjustments to achieve the desiredgroup disparity and running length.

FIG. 11 is a flowchart 1100 showing a method of generating testsequences according to one exemplary embodiment. The method acts shownin FIG. 11 can, in certain circumstances, be performed in a differentorder, or performed alone or in various combinations and subcombinationswith one another.

At 1110, the unconstrained test sequence (for example, the unconstrainedworst case sequence generated using Expression (3) above) is dividedinto bit groups and the location of the first group to generate in thetest sequence is determined. Defining the first group (and, as discussedbelow, choosing the initial disparity) is a choice that can produce anoverall reduction in the number of changes to the unconstrained group.For example, the initial running disparity of the first group isdesirably selected so as to minimize (or otherwise reduce) the overallnumber of changes to the unconstrained test sequence. After the firstgroup is chosen at 1110, the running disparity constraint will beconsidered, meaning that there is less choice in selecting thesubsequent groups.

In one desirable embodiment, the group that corresponds to values havingthe greatest magnitude (by bit group) in the pulse response andexcluding the leading bit is selected as the initial bit group.Typically, the group with values having the greatest magnitudes is thefirst post-leading-bit group (that is, the group of samples thatdirectly follow the main (leading) bit). For the exemplary invertedresponse introduced above in FIG. 3, for instance, the group with valueshaving the greatest magnitude is formed from the samples preceding themain bit. Specifically, the first group is selected to comprise the bitsat positions n=17 . . . 12 and is designated as group 1 in the fourthcolumn of Table 1. Note that in this example, a first group of 6 bitswas selected, although a group of 4 bits would also have been a validchoice and could alternatively have been selected. In certainimplementations, the sequence generating technique 1100 is performedmultiple times (for example, using all possible initial selections orany subset thereof), and the worst of the generated solutions selected.

At 1112, the first group is evaluated for compliance with thetransmission code and modified if necessary. In one embodiment, thefewest changes possible are made to the group in order for it to complywith the transmission code. Techniques for modifying the group arediscussed in more detail below with respect to method act 1114. In thisexample, the first group is already compliant with the 8b10btransmission code and no further modifications are necessary.

In this example, the first group (comprising “+−−++−” in theunconstrained solution) is initially considered neutral. In certainembodiments, its disparity can be left as neutral. Or, in someembodiments, when the first group is neutral, it is possible todesignate the group as either having a positive or negative initialdisparity. This selection can be made, for example, once the firstbiased group is encountered during application of the technique 1100 asshown by method act 1114 and can be selected so as to minimize or reducethe modifications made to the biased group or later-considered groups.In the illustrated embodiment, method act 1114 is typically onlyperformed once (when the first biased group is encountered and assignified by the dashed lines in FIG. 11) and may be performedconcurrently with method act 1116.

At 1116, the next bit group of the unconstrained test sequence isevaluated for compliance with the transmission code and modified ifnecessary. For example, the illustrated embodiment proceeds toward thefront of the sequence, though other embodiments proceed in the oppositedirection. In this example, the next group is group 2 shown in Table 1having indexes 8-11. The 4 bits of the unconstrained group have thefollowing polarities: “++++.” This is not a valid group in the protocol.Since the pre-existing disparity has not yet been defined, one canselect the initial disparity at 1114 as being negative (for example, inorder to allow for more “1”s in group 2). This running disparity value(“−1”) is desirably stored, as it will be used when the top of the tableis reached and the technique continues from the group beginning at n=18.In order to comply with the constraints introduced above, one of the “+”bits in the group with indexes 8-11 is desirably replaced by a “−.” Inone exemplary implementation, the “+” bit to change is selected so as tofurther reduce (for example, minimize) the impact to the resulting eyeopening in an eye diagram. For example, Expression (3) can be used todetermine which bit should have its polarity reversed. In certainembodiments, the smallest impact is produced if the sign correspondingto the smallest pulse response sample value in the group is selected.Here, for example, this value is 0.001 at n=8. Group 2 is now defined,and the running disparity is changed to positive (“+1”).

At 1118, a determination is made as to whether any further bit groupsremain to be evaluated. If so, the technique 1100 returns to 1114, wherethe next bit group is evaluated. Otherwise, the technique 1100terminates. In the illustrated embodiment, group 3 (indexes 2-7) isevaluated next. Group 3 is a group of 6 bits all being logical “0”s or“−”s. This is not a valid 8b10b group according to the constraintsintroduced above. Since the running disparity is positive, a group withnegative disparity (“−2”) can be selected. In this example, two bits ofgroup 3 are desirably converted into positive bits in order to complywith the disparity constraints. As before, the smallest samples withinthe group are selected. In the illustrated example, these are numbersn=2 and 7. Group 3 is now defined, and the running disparity is changedto negative (“−1”).

In the illustrated example, the technique 1100 has now reached the topof the unconstrained sequence in Table 1 and the top group is initiallyincomplete. In one desirable implementation, the samples are extended atthe top (or bottom) of the table with zero values. Such extensions willnot ordinarily affect the result estimated by Expression (3). The groupwith missing bits can therefore be built up as needed, by consideringthe existing and desired disparity. In the illustrated example, forinstance, group 4 is filled with “+” bits in order to maintain theconstraint that the groups have alternating disparity. Group 4 is nowdefined, and the running disparity is changed to positive (“+1”). Group4 could alternatively have been filled with two positive bits and anegative bit, resulting in a neutral group.

In one implementation, the technique 1100 considers the bits at the endof the sequence (the bottom of the table) once the top is reached,though these bits could have been considered at any time after theinitial group is determined. In the illustrated example, the bits havingindexes 18-20 form an incomplete group. This group can be extended byadding one or more zero samples. In this example, the pre-existingdisparity selected for group 1 was negative. Hence, group 5 can eitherbe neutral or negative. Both are possible and no modification isrequired. In the illustrated example, a group with negative disparity isselected and the running disparity is modified accordingly. Now, withthe running disparity updated, the technique could continue moving downthe table if required.

The constraints applied in the exemplary technique 1100 described abovecan be summarized in a more formal fashion as shown in Table 2.

TABLE 2 Logical ‘ones’ to be replaced with ‘zeros’ Pre-existing runningGroup disparity disparity −6 −4 −2 0 +2 +4 +6 −1 −3 −2 −1 0 0 1 2 0 (notyet initialized) −2 −1 0 0 0 1 2 +1 −2 −1 0 0 1 2 3

For each possible value of the group disparity and pre-existing runningdisparity, Table 2 shows the number of bits in which “1”s should bechanged into “0”s (or the reverse, if the number is negative). Forexample, let the running disparity be “−1” and the next (or subsequent)group be “001001”. This next group's self disparity is −2 (−4+2=−2).From the first row and third column, a change of “−1” is desirable tocomply with the 8b10b constraints. Thus, one 0-to-1 transformation canbe used to make the bit group neutral. If the pre-existing runningdisparity for the same group is positive (“+1”), then Table 2 indicatesthat the group can remain unchanged, resulting in a running disparityequal to “−1” (+1−2=−1).

In the example described above, no modifications were required onaccount of an excessive running length. However, running “1”s violationscan occur, for example when concatenating the following group pairs fromthe 8b10b protocol:

[001111][1100]→P6/Z4 (6-bit group with positive disparity, 4-bit withzero disparity)

[000111][1110]→Z6/P4 [0011][111100]→Z4/P6

Note that all of the above groups are either of the PZ or ZP type.Therefore, the pre-existing disparity could only be negative. With anegative pre-existing disparity, the subsequent groups could be one ofthe following: ZZ, PZ, ZP, PN (here N stands for negative groupdisparity). To reduce the impact from changing logical bit values, thenumber of group types changed can be minimized in certain desirableimplementations of the disclosed technology. For example, if a running“1” violation is detected, the combinations PZ can be changed into ZZ orPN, depending on whichever group contains the smallest sample value thatcorresponds to the bit in the group of logical “1”s. Further, thecombination ZP can be changed into ZZ.

Similar considerations can be made for running “0” violations. Forexample, in certain implementations, the solutions for running “0”violations are found by swapping “0”/“1” and “P”/“N” in the abovediscussion.

In general, the exemplary technique described above modifies theunconstrained worst case sequence to comply with the 8b10b protocol. Forexample, in the embodiment illustrated by Table 1, each 6- or 4-bitgroup was modified so as to minimize the difference between theconstrained and the original unconstrained sequence. Minimization wasmade locally for each group without considering possible consequencesfor the groups to follow. Although the technique produces high qualityworst-case sequences, the technique may not produce the worst casesequence. The second illustrative embodiment is an alternative methodand does not modify the unconstrained worst case sequence.Implementations of the second illustrative embodiment produce evenhigher quality worst case sequences. For example, higher quality resultscan be obtained by considering the impact of a bit group globally in thesequence rather than locally. Certain implementations of the secondillustrative embodiment are understood to produce the theoretical “worstcase” sequence.

SECOND ILLUSTRATIVE EMBODIMENT

Given a linear time-invariant signal channel characterized by its pulseresponse, and the duration of the bit interval, another embodiment ofthe disclosed technology can be used to generate a binary pattern of agiven length that complies with the 8b10b transmission protocol andcreates the worst case sequence for testing signal integrity and biterror rates. For example, the sequences generated can produce the worstor near worst eye openings on an eye diagram (often used to provide avisual display of the signal quality on a channel being analyzed overmany transitions).

In certain exemplary implementations, the test sequence generationtechnique uses the inverted sampled pulse response Q(k), k=1 . . . N asinput. The inverted sampled pulse response is discussed in more detailabove. As with the implementations described above, it should beunderstood that the noninverted sampled pulse response can be used withany of the test sequence generation methods described herein. In suchcases, the direction in which the test sequence is generated relative topulse response will ordinarily be reversed.

Briefly, and according to one exemplary embodiment, the test sequence tobe generated is first represented by a chart (or other appropriate datastructure, model, table, or representation) indicating possible codeword types (and accounting for possible word length and pre- andpost-word disparity constraints) and the allowed transitions betweenthem. Then, for one or more code word types, a candidate code word isselected (for example, the “worst” candidate) from the code word tableby estimating its individual “cost.” Individual costs can be estimatedby element-by-element multiplication of the word bit values (forexample, “+1” or “−1”) with the corresponding portion of the sampledpulse response. If the current portion of the response contains theleading sample, the set of considered code words can be limited to thosethat contain “1” in the corresponding position.

A forward and backward sweep can be performed along the word sequence.In certain exemplary implementations, the forward sweep finds the“worst” choice (or other desirably bad choice) between the possible wordtypes in each word position. In certain desirable implementations, thischoice is based on estimating the cumulative cost (for example, the sumof the individual cost and the cumulative cost from a respective word's“worst” predecessor). From the forward sweep, the final “worst” word ina sequence can be determined and its type defined.

The backward sweep is performed to identify the chain of predecessorsthat led to the final “worst” word. Among several cost values, forexample, the “worst” choice can be determined by selecting the smallestvalue. As a result, the generated sequence produces a desirably small(and in some implementations, the smallest) product of the bit valuesand sampled pulse response, and thus produces a small (for example, theminimum) eye-height measure. Additional details of these individualmethod acts are described in the sections below.

8b10b Protocol Code Word Types and Tables

To represent the possible 8b10b coding words (also referred to as codewords, bit groups, or groups) and their allowed transitions, eachpossible 8b10b coding word (or other desirable number of coding words)can be categorized into a fixed number of types. For example, in oneexemplary implementation, a type is defined by a self disparity, and aresulting (post) disparity. For purposes of this discussion, apre-existing disparity is denoted with a small prefix “n” (negative) or“p” (positive). The self-disparity, which may be P (positive), N(negative), or Z (zero) complemented by the group length, is set forthin the middle of the code word type. The postfix (“n” or “p”) shows theresulting running disparity. For example, the type “nP6p” is a 6-bitgroup with a negative pre-existing disparity, a positive self disparity,and a positive post-running disparity.

In general, for the 8b10b protocol, there are only eight group typesavailable: nP6p, pN6n, nZ6n, pZ6p and nP4p, nZ4n, pN4n, pZ4p. Althoughthe exemplary techniques described herein are not sensitive to theparticular code words allowed for each group type, code words for eachgroup type according to the 8b10b transmission code are shown in Table 3for illustrative purposes.

TABLE 3 8b10b Code Words Used in Different Word Types NN nP6p pN6n nZ6npZ6p nP4p pN4n nZ4n pZ4p 1 011011 100100 110001 110001 1011 0100 10011001 2 111010 000101 101001 101001 1101 0010 0101 0101 3 110110 001001011001 011001 1110 0001 1010 1010 4 001111 110000 100101 100101 01111000 0110 0110 5 101110 010001 010101 010101 1100 0011 6 011110 100001110100 110100 7 101011 010100 001101 001101 8 100111 011000 101100101100 9 011101 100010 011100 011100 10 101101 010010 100011 100011 11110101 001010 010011 010011 12 111001 000110 110010 110010 13 010111101000 001011 001011 14 110011 001100 101010 101010 15 011010 011010 16100110 100110 17 010110 010110 18 001110 001110 19 111000 000111

Note that group types with neutral disparity and the same size may havecommon words. Most of the nZ6n and pZ6p words are similar, except forthe last row. The same is true for nZ4n and pZ4p types. The reason thedistinction was introduced between these neutral groups was to preventrunning length violations. For example, after the “positive” word“001111,” the neutral word “0011” (type pZ4p) may follow, but not theneutral word “1100” (type nZ4n) which would create six “1”s in a row.

Code Word Type Transition Chart

Using definitions such as those introduced above, rules can beformulated that indicate how the code word types may precede and followeach other according to any given transmission code (for example, the8b10b transmission code). For example, the available transitions betweenthe code word types introduced above and for one exemplaryimplementation are shown in FIG. 4. In particular, FIG. 4 is a schematicblock diagram 400 showing the various possible code word types 410 alongwith the possible transitions between the code word types (shown byarrows 412). For ease of illustration, only a few representative samplesof the code word types 410 and arrows 412 are designated in FIG. 4.FIGS. 5, 6, and 7 similarly call out only a few representative code wordtype representations.

The rules followed by the exemplary implementation illustrated in FIG. 4are derived from the constraints introduced above and comprise thefollowing: (1) the resulting disparity of a word (indicated by itspostfix according to the format introduced in the previous section) mustbe equal to the pre-existing disparity of the next code word type(indicated by the code word's prefix), and the code word lengths (6 or 4bits) must alternate. Note that in this exemplary implementation, eachcode word type has two possible predecessors and two possible successorcode word types.

As in the first representative embodiment, one goal to be achieved inexemplary implementations of the second representative embodiment is toreduce (or minimize) the relation:

$\begin{matrix}{{\min \left( {y(N)} \right)} = {\min {\sum\limits_{n = 1}^{N}{{Q(n)}{x(n)}}}}} & (6)\end{matrix}$

by appropriately choosing the code words constituting the binarysequence x(n). In Expression (6), Q(n) is the inverted sampled pulseresponse (as described above) for a channel under consideration. Ingeneral, the bit elements in x(n) can be chosen, but not in Q(n). Inaddition, a certain predefined bit of an index n_(max), can be assumedto be a logical “1”. Thus, x(n_(max)) can be fixed to the logical “1”.

To illustrate the exemplary procedure, assume that a 6-bit group ischosen as the starting group for the sequence so that the sequence ofgroups constituting x(k) along with the response Q(k) can be arranged asin schematic block diagram 500 shown in FIG. 5. In particular, thediagram 500 of FIG. 5 includes a region 510 in which representationsshowing the values of the sampled pulse response in the correspondinggroup position Q_(i) are displayed. These representations are referredto herein as pulse response groups 512.

In FIG. 5, the group Q_(i) (a 4-bit group) is shown as having theleading bit position. In particular, frame 514 is a representationshowing the location of the leading bit within the code word typerepresentations 522 corresponding to group Q_(i). The leading bit (forexample, the bit in the inverted sampled pulse response with thegreatest value) can be oriented at other bit positions within the testsequence. For the 8b 10b transmission code, for example, there are 10different choices for how to orient the leading bit, as a pair ofadjacent groups consists of 10 bits. In certain implementations, theprocedure described below can be repeated for each such startingposition (or for other numbers of the positions) in order to find the“worst” possible sequence. Furthermore, to make the terminal groupscomplete, and in certain exemplary implementations, a certain number ofzero samples can be added at the beginning and/or at the end of aresponse Q(k).

At this point, the groups in Q(k) and x(k) can be assumed to be alignedand the position of the leading bit (and the group containing it)defined. From the resulting sequence of groups, a starting group (Q₁)can be identified (corresponding to the group Q₁ having the first valuesof the inverted sampled pulse response).

FIG. 5 also shows a code word region 520 that includes representationsof the possible code word types that may be selected to create theworst-case sequence. A sample of these representations is shown as codeword type representations 522. Conceptually, the representation 522 inFIG. 5 can be viewed as placeholders for four different types of codeswords for each position i. In this example, each code word typerepresentation 522 allows for storing its available predecessors, itsoptimal predecessor, its local cost value, a cumulative cost value, andits local (6- or 4-bit long) code word (or bit pattern).

FIG. 12 is a flowchart 1200 showing one exemplary implementation forgenerating the worst-case sequence according to the disclosedtechnology. The method shown in FIG. 12 is performed using a chart, datastructure, model, table, or representation arranged according to theformat introduced above with respect to FIG. 5. Thus, the procedure 1200assumes that a starting position has already been determined. As notedbelow, however, the procedure can be performed for each possiblestarting position, thereby creating different starting positions, andthe overall worst sequence selected from the various results obtained.The method acts shown in FIG. 12 can, in certain circumstances, beperformed in a different order, or performed alone or in variouscombinations and subcombinations with one another.

At 1210, local costs for each of the possible code word typerepresentations can be determined. In particular, in one implementation,local optimums can be found for each index position i for each code wordtype at a respective index position (in alternative embodiments, only asubset of the index positions or code word types are considered). Thisact is performed because it is typically not yet known which code wordtype will be selected in every position. In one exemplaryimplementation, this method act can be performed by minimizing therelation

$\begin{matrix}{{{cost}\left( {j,{type}} \right)} = {y_{j,{type}} = {\sum\limits_{i = 1}^{4\mspace{11mu} {or}\mspace{11mu} 6}{{Q_{j}(i)}{x_{j,{type}}(i)}}}}} & (7)\end{matrix}$

by choosing from Table 3 the optimal code word for a certain type. Thevalue determined can be obtained using the choice from Table 3 thatminimizes (or otherwise reduces to a desirable level) Expression (7) andcan be designated as a local cost for that code word type at itscorresponding position. Conceptually, the local cost is a valueindicative of how much a code word of a selected code word type impactsor alters the output of the channel when the code word is included inthe test sequence.

At 1212, cumulative costs can be determined for the possible cord wordtypes. In one implementation, for every code word at every position, acumulative cost and its optimal predecessor can be determined. Forexample, in one particular implementation, this method act comprisesperforming a sweep from left to right (or right to left). For the firstcode word position considered (for example, the leftmost groups), thecumulative cost of each code word type is its own cost computed at 1210.For the next positions, i=2 . . . M, the cumulative cost of a code wordtype can be defined as a sum of its own local cost plus the smallestcumulative cost from its two available predecessors. At this point, thecode word type representation stores an identity of its predecessor (ora pointer to it) having the smallest cumulative cost (for example, bymarking it as the “best” candidate predecessor). Conceptually, thecumulative cost for a code word type representation is a valueindicative of how much a sequence of code words that includes the localbit group and one or more sequentially related bit groups (if any)impacts or alters the output of the channel when the sequence of codewords is included in the test sequence.

At 1214, once the initial sweep is complete, the code word typerepresentations 522 in the last position will contain cumulative coststhat are “global” for the full test sequence being generated. From thefour available alternatives, the code word type representation with thesmallest cost can be identified. In this exemplary implementation, thiselement will belong to the chain of code word type representationsconstituting the worst sequence. Because predecessors were marked foreach code word type representation during computation of the cumulativecosts, the chain of code words that led to that result can be restoredat 1214. In this embodiment, the restored chain defines the worst casesequence.

Method acts 1210, 1212, 1214, can be repeated for other possible leadingbit orientations. For example, the acts can be repeated for all thepossible leading bit positions (or a subset thereof) in order to findbetter solutions, such as the globally optimal solution.

In the method acts 1210 and 1212, the local costs of predecessors mayoccasionally become equal. In such situations, and in certainimplementations of the disclosed technology, any of the predecessors canbe selected. This selection typically does not affect the quality of theworst case sequence but only indicates that there are several sequencesthat produce equally closed eye diagrams. If desired, the technique canbe modified so that all such possible sequences are generated andconsidered.

In the following paragraphs, an exemplary application of methods acts1210, 1212, and 1214 is described. Assume for purposes of this examplethat the inversed pulse response contains 20 samples with sample valuesas shown in Table 4. In Table 4, the leading (sample) value is shown inbold.

TABLE 4 Example Inverted Pulse Response Q(n)

For method act 1212, it can be observed that any code group x_(i,type),standing in a position i and having the type type={nP6p, pN6n, nZ6n,pZ6p and nP4p, nZ4n, pN4n, pZ4p} can be replaced with another group fromTable 1 having the same type, without any consequence from the disparityand running length rules.

FIG. 6 is a schematic block diagram 600 in the form of the diagram 500in FIG. 5 and shows the result of method act 1212 for this example. Inparticular, the code word type representations 622 in the code wordregion 620 show the selected code word (selected from Table 3) and thelocal cost of each selected code word. In this example, for eachparticular 6- or 4-bit portion of the response Q, (Q_(i), i=1 . . . 4)and each possible code word type (nPp, pNn, nZn or pZp), the word thatmakes the smallest local cost as defined by Expression (7) can be foundfrom Table 3. For example, of the code words corresponding to responsegroup Q₁=[−0.08, 0.11, 0.16, 0.09, 0.01, −0.07], the code word “100111”creates the smallest cost among words of type nPp and size 6. Rememberthat in Expression (7), a logical “1” means taking the value with sign“+” and logical “0” means taking the value with sign “−”. Hence, thelocal cost for this word in this position is defined as:

Cost(1,nPn)=(−0.08)−(0.11)−(0.16)+(0.09)+(0.01)+(−0.07)=−0.32  (8)

It is easy to verify that no other code word of this type and in thisposition gives a smaller cost.

In certain implementations, the response group that contains the“leading bit” is treated differently. In this example, assume that theleading bit (shown by frame 614) is the 5-th bit in the third pulseresponse group (Q₃). For this position, when looking for a word with thesmallest cost, those without a logical “1” in the leading bit positionare ignored. Note, for instance, that all code words corresponding topulse response group Q₃ of this example have a logical “1” at the fifthbit.

At this point, method act 1212 is considered complete. The fragments ofthe worst case sequence are already defined, although alternatives mayexist concerning how to combine the fragments together.

For method act 1214, it is known that each code word may have twodifferent predecessors as was illustrated by FIG. 4. One of thepredecessors, however, may have a smaller cumulative cost, defined asthe sum of its own cost and the cumulative cost of its best predecessor.

The procedure of establishing the cumulative cost and best predecessorsaccording to one exemplary implementation is illustrated by schematicblock diagram 700 shown in FIG. 7. Block diagram 700 also has the formof the diagram 500 in FIG. 5. Starting the process from left to right(though the procedure may similarly be performed from right to left orother sequences, with equally good results), for the leftmost code wordtype representations 722 in the code region 720 (corresponding to thepulse response group Q₁), the cumulative costs are defined (shownunderlined and bolded) and are equal to their local costs (shown inparentheses). In the next column (second from the left and correspondingto the pulse response group Q₂), the local cost is already known but notthe cumulative cost. Each code word type representation may have twopredecessors, as indicated by the arrows. However, in this exemplaryimplementation, the predecessor having the smallest cumulative cost isselected. According to one exemplary embodiment, the cumulative cost canbe defined as:

Cum. cost=local cost+cum. cost of the best predecessor.  (9)

For example, the code word type representation nZn of size 4 in thesecond column (corresponding to response Q₂) has a local cost of −0.19.It also has two predecessors: pNn in the first column (corresponding toresponse group Q₁) with cumulative cost −0.52, and nZn in the firstcolumn with a cumulative cost −0.50. The first code word typerepresentation (pNn) has the smallest cumulative cost. Therefore, it ismarked as the best predecessor for the code word type representationnZn, and its cumulative cost is used to find the cumulative cost of thecode word type representation nZn: cum. cost of (nZn,2)=−0.19-0.52=−0.71. At the end of the sequence (here, at the fourthcolumn corresponding to response group Q₄), the final cumulative costsare determined.

At method act 1214, the smallest cumulative cost (“−0.28”) is identifiedas belonging to the code word type representation nPp in the finalcolumn. The sequence order that led to this code word typerepresentation can then be restored. The restoration process in theillustrated implementation is straightforward because the preferredpredecessors have all been marked (for example, using pointers). FIG. 7illustrates the preferred predecessors through undashed arrows. Thechain of code word type representations producing the worst casesequence can therefore be restored with a reverse sweep (from right toleft), which produces the following sequence:

pN6n→nP4p→pN6n→nP4p

The bit content of the representations was already defined during methodact 1212, as shown in FIG. 6. Combining the bits together, the followingworst sequence is generated:

100001 1110 000110 0111

Note that this sequence represents the solution for a particularstarting bit choice. The method acts 1212, 1214, 1216 can be repeatedfor multiple other starting positions in order to find a globalsolution. To do so, it may be necessary to add a few zero samples foralignment.

Exemplary Computing Environments

Any of the aspects of the technology described above may be performedusing a distributed computer network. FIG. 8 shows one suitableexemplary network. A server computer 800 can have an associated storagedevice 802 (internal or external to the server computer). For example,the server computer 800 can be configured to generate test sequencesusing any of the disclosed methods (for example, as part of an EDAsoftware tool, such as a signal integrity analysis tool). The servercomputer 800 can be coupled to a network, shown generally at 804, whichcan comprise, for example, a wide-area network, a local-area network, aclient-server network, the Internet, or other suitable network. One ormore client computers, such as those shown at 806, 808, may be coupledto the network 804 using a network protocol. The work may also beperformed on a single, dedicated workstation, which has its own memoryand one or more CPUs.

FIG. 9 shows another exemplary network. One or more computers 902communicate via a network 904 and form a computing environment 900 (forexample, a distributed computing environment). Each of the computers 902in the computing environment 900 can be used to perform at least aportion of the sequence generating process. The network 904 in theillustrated embodiment is also coupled to one or more client computers908.

FIG. 10 shows that design information for a circuit or PCB design (forexample, a PCB layout file (such as a .HYP file), an HDL file, netlist,GDSII file, Oasis file, or other suitable design file representing thecircuit or PCB-under-test) can be analyzed using a remote servercomputer (such as the server computer 800 shown in FIG. 8) or a remotecomputing environment (such as the computing environment 900 shown inFIG. 9) in order to generate a test sequence according to any of thedisclosed embodiments. At process block 1002, for example, the clientcomputer sends the design information to the remote server or computingenvironment. In process block 1004, the design information is receivedand loaded by the remote server or by respective components of theremote computing environment. In process block 1006, test sequencegeneration is performed according to any of the disclosed embodiments.At process block 1008, the remote server or computing environment sendsthe resulting test sequences to the client computer, which receives thedata at process block 1010.

It should be apparent to those skilled in the art that the example shownin FIG. 1000 is not the only way to generate test sequences usingmultiple computers. For instance, the circuit or PCB design informationmay be stored on a computer-readable medium that is not on a network andthat is sent separately to the server or computing environment (forexample, a CD-ROM, DVD, or portable hard drive). Or, the server computeror remote computing environment may perform only a portion of the testsequence generation procedure.

Having illustrated and described the principles of the disclosedtechnology, it will be apparent to those skilled in the art that thedisclosed embodiments can be modified in arrangement and detail withoutdeparting from such principles. In view of the many possible embodimentsto which the principles of the disclosed technologies can be applied, itshould be recognized that the illustrated embodiments are only preferredexamples of the technologies and should not be taken as limiting thescope of the invention. Rather, the scope of the invention is defined bythe following claims and their equivalents. I therefore claim as myinvention all that comes within the scope and spirit of these claims.

1. A method of generating a test sequence of bits for testing theelectrical behavior of a circuit channel, comprising: dividing a sampledpulse response for the circuit channel into a series of bit groups, therespective lengths of the bit groups in the series complying with atransmission code; determining possible code word types corresponding tothe bit groups of the sampled pulse response, the possible code wordtypes also complying with the transmission code; computing cumulativecosts for one or more of the possible code word types, the cumulativecost for a respective code word type indicating how effective a sequencecomprising a code word of the respective code word type together withone or more other code words is at altering the intended output of thecircuit channel when the sequence is included in the test sequence;generating the test sequence by selecting a sequence of code words basedat least in part on the determined cumulative costs; and storing thetest sequence on one or more computer-readable media.
 2. The method ofclaim 1, further comprising computing local costs for the one or more ofthe possible code word types, the local cost for a respective code wordtype indicating how effective a code word of the respective code wordtype is at altering an intended output of the circuit channel when thecode word is included in the test sequence.
 3. The method of claim 2,wherein the cumulative cost for the respective code word type iscomputed in part from local costs of the other code words in thesequence.
 4. The method of claim 2, wherein the act of computing thelocal costs comprises evaluating possible code words of a respectivecode word type to determine which of the possible code words producesthe lowest local cost for that respective code word type.
 5. The methodof claim 1, wherein the act of determining the cumulative costs includesdetermining cumulative costs of sequences that represent full testsequences, and wherein the act of generating the test sequence comprisesselecting the full test sequence producing the lowest cumulative cost.6. The method of claim 1, wherein the code word of the respective codeword type is a first code word in the sequence and wherein the act ofcomputing cumulative costs comprises selecting a second code word to besequentially adjacent to the first code word from among multiplepossible second code words, the multiple second code words being of codeword types different than the first code word.
 7. The method of claim 6,wherein the method further comprises: determining allowable transitionsbetween the possible code word types; and determining the multiplepossible second code words based at least in part on the determinedallowable transitions.
 8. The method of claim 6, wherein the multiplepossible second code words have associated cumulative costs and whereinthe selection comprises selecting the second code word having the lowestassociated cumulative cost.
 9. The method of claim 1, wherein the act ofdividing includes orienting the bit groups in a first orientationrelative to a leading bit in the sampled pulse response, the methodfurther comprising repeating the acts of dividing, determining, andcomputing for one or more other bit group orientations relative to theleading bit.
 10. The method of claim 1, further comprising: simulatingapplication of a single pulse applied to the circuit channel, therebygenerating a pulse response; and dividing the pulse response intosamples, thereby generating the sampled pulse response, the samplesbeing determined according to a bit rate at which the circuit channel isto operate.
 11. The method of claim 1, wherein the transmission code isthe 8b 10b transmission code.
 12. The method of claim 1, wherein thesampled pulse response is an inverted sampled pulse response.
 13. Themethod of claim 1, wherein the test sequence minimizes an eye opening ofan eye diagram that displays a representation of the circuit channel'sresponse to the test sequence.
 14. One or more computer-readable mediastoring computer-executable instructions for causing a computer toperform the method of claim
 1. 15. One or more computer-readable mediastoring a test sequence generated by the method of claim
 1. 16. Amethod, comprising: nonrandomly determining a sequence of code words tobe input on a circuit channel, the sequence of code words complying witha transmission code and being designed to cause the output voltage ofthe channel to be reduced during a time period in which the channeloutputs a logic high value; and storing the sequence on one or morecomputer-readable media.
 17. The method of claim 16, wherein the act ofnonrandomly determining the sequence comprises dividing a sampled pulseresponse for the circuit channel into bit groups, the bit groups havinglengths complying with the transmission code.
 18. The method of claim17, wherein the act of nonrandomly determining the sequence furthercomprises identifying possible code word types for the bit groups of thedivided sampled pulse response.
 19. The method of claim 16, wherein theact of nonrandomly determining the sequence comprises computing a valueindicative of the impact a candidate code word has on reducing theoutput voltage of the circuit channel when the candidate code word isincluded in the sequence.
 20. The method of claim 16, wherein the act ofnonrandomly determining the sequence comprises computing a valueindicative of the impact a subsequence of code words has on reducing theoutput voltage of the circuit channel when the subsequence of code wordsis included in the sequence.
 21. The method of claim 16, wherein the actof nonrandomly determining the sequence comprises: evaluating a codeword in the sequence; and selecting a sequence of code words to precedethe code word from among multiple possible sequences of code words, theselection being based at least in part on the impact a respective one ofthe multiple possible sequences has on the output voltage of the circuitchannel when the respective one of the multiple possible sequences isincluded in the sequence.
 22. The method of claim 16, wherein the act ofnonrandomly determining the sequence comprises: evaluating individualcode words for possible inclusion in the sequence; and selecting one ormore of the code words for inclusion in the sequence based at least inpart on the effect the one or more of the code words have on the outputvoltage of the circuit channel when the code words are included in thesequence.
 23. The method of claim 16, wherein the transmission code isthe 8b10b transmission code.
 24. The method of claim 16, wherein thesequence of code words is the worst case sequence.
 25. The method ofclaim 16, wherein the sequence of code words minimizes an eye opening ofan eye diagram that displays a representation of the circuit channel'sresponse to the sequence of code words.
 26. One or morecomputer-readable media storing computer-executable instructions forcausing a computer to perform the method of claim
 16. 27. One or morecomputer-readable media storing the sequence generated by the method ofclaim
 16. 28. A method of generating a test sequence of bits for testingthe electrical behavior of a circuit channel, comprising: dividing atest sequence unconstrained by any transmission code into a series ofbit groups, the lengths of the bit groups in the series complying with atransmission code; evaluating a first bit group in the series forcompliance with the transmission code; if the first bit group isdetermined not to comply with the transmission code, modifying one ormore bits in the first bit group so that the first bit group complieswith the transmission code; and storing the modified first bit group onone or more computer-readable media.
 29. The method of claim 28, furthercomprising: evaluating a second bit group in the series for compliancewith the transmission code, the second bit group being adjacent to thefirst bit group in the series; if the second bit group is determined notto comply with the transmission code, modifying one or more bits in thesecond bit group so that the second bit group complies with thetransmission code; and storing the modified second bit group on the oneor more computer-readable media.
 30. The method of claim 29, wherein thefirst bit group has a neutral disparity, and wherein the method furthercomprises determining an initial disparity for the first bit group, thedetermination being based at least in part on a disparity of the secondbit group.
 31. The method of claim 28, further comprising: sequentiallyevaluating the remaining bit groups in the series for compliance withthe transmission code; modifying respective ones of the remaining bitgroups if they do not comply with the transmission code; and storing themodified bit groups on the one or more computer-readable media.
 32. Themethod of claim 28, further comprising generating the test sequenceunconstrained by any transmission code.
 33. The method of claim 32,wherein the act of generating the test sequence unconstrained by anytransmission code comprises: simulating application of a single pulseapplied to the circuit channel, thereby generating a pulse response;dividing the pulse response into samples, thereby generating a sampledpulse response, the samples being determined according to a bit rate atwhich the circuit channel will operate and having a polarity and amagnitude; and assigning test sequence bits having polarities oppositeto the polarities of corresponding samples in the sampled pulseresponse.
 34. The method of claim 28, wherein the first bit groupcorresponds to a position in the test sequence adjacent to the largestvalue in a sampled pulse response of the channel.
 35. One or morecomputer-readable media storing computer-executable instructions forcausing a computer to perform the method of claim
 28. 36. One or morecomputer-readable media storing the test sequence generated by themethod of claim 28.